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DATA SHEET
For a complete data sheet, please also download:
* The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4076B MSI Quadruple D-type register with 3-state outputs
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
Quadruple D-type register with 3-state outputs
DESCRIPTION The HEF4076B is a quadruple edge-triggered D-type flip-flop with four data inputs (D0 to D3), two active LOW data enable inputs (ED0 and ED1), a common clock input (CP), four 3-state outputs (O0 to O3), two active LOW output enable inputs (EO0 and EO1), and an overriding asynchronous master reset input (MR).
HEF4076B MSI
Information on D0 to D3 is stored in the four flip-flops on the LOW to HIGH transition of CP if both ED0 and ED1 are LOW. A HIGH on either ED0 or ED1 prevents the flip-flops from changing on the LOW to HIGH transition of CP, independent of the information on D0 to D3. When both EO0 and EO1 are LOW, the contents of the four flip-flops are available at O0 to O3. A HIGH on either EO0 or EO1 forces O0 to O3 into the high impedance OFF-state. A HIGH on MR resets all four flip-flops, independent of all other input conditions.
Fig.2 Pinning diagram.
HEF4076BP(N): 16-lead DIL; plastic (SOT38-1) HEF4076BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4076BT(D): 16-lead SO; plastic (SOT109-1) Fig.1 Functional diagram. ( ): Package Designator North America
PINNING D0 to D3 ED0, ED1 EO0, EO1 CP MR O0 to O3 data inputs data enable inputs (active LOW) output enable inputs (active LOW) clock input (LOW to HIGH, edge-triggered) master reset input data outputs
FAMILY DATA, IDD LIMITS category MSI See Family Specifications
January 1995
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Philips Semiconductors
Product specification
Quadruple D-type register with 3-state outputs
HEF4076B MSI
Fig.3 Logic diagram.
January 1995
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Philips Semiconductors
Product specification
Quadruple D-type register with 3-state outputs
FUNCTION TABLE INPUTS MR H L L L L L CP X ED0 X H X L L X ED1 X X H L L X Dn X X X H L X OUTPUTS On L no change no change H L no change Notes
HEF4076B MSI
1. EO0 = EO1 = LOW When either EO0 or EO1 is HIGH, the outputs are disabled (high impedance OFF-state). H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition = negative-going transition
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns; see also waveforms Fig.4 VDD V Propagation delays CP On HIGH to LOW 5 10 15 5 LOW to HIGH MR On HIGH to LOW Output transition times HIGH to LOW 10 15 5 10 15 5 10 15 5 LOW to HIGH 3-state propagation times Output disable times EOn On HIGH LOW 5 10 15 5 10 15 tPLZ tPHZ 50 35 30 45 30 30 105 70 65 90 65 60 ns ns ns ns ns ns 10 15 tTLH tTHL tPHL tPLH tPHL 150 60 45 160 65 45 95 40 30 60 30 20 60 30 20 305 120 85 320 130 90 190 85 65 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 123 ns + (0,55 ns/pF) CL 49 ns + (0,23 ns/pF) CL 37 ns + (0,16 ns/pF) CL 133 ns + (0,55 ns/pF) CL 54 ns + (0,23 ns/pF) CL 37 ns + (0,16 ns/pF) CL 68 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA
January 1995
4
Philips Semiconductors
Product specification
Quadruple D-type register with 3-state outputs
HEF4076B MSI
TYPICAL EXTRAPOLATION FORMULA ns ns ns ns ns ns
VDD V Output enable times EOn On HIGH LOW 5 10 15 5 10 15
SYMBOL
MIN.
TYP. 65
MAX. 130 55 40 120 50 35
tPZH
30 20 60
tPZL
25 20
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Set-up times Dn CP 5 10 15 5 EDn CP Hold times Dn CP 10 15 5 10 15 5 EDn CP Minimum clock pulse width; LOW Minimum MR pulse width; HIGH Recovery time for MR Maximum clock pulse frequency 10 15 5 10 15 5 10 15 5 10 15 5 10 15 fmax tRMR tWMRH tWCPL thold thold tsu tsu SYMBOL MIN. 10 0 0 0 0 0 55 20 15 25 10 5 120 45 30 55 30 20 90 35 20 4 11 16 TYP. -15 -10 -5 -50 -20 -15 30 10 10 -25 -10 -5 60 20 15 25 15 10 45 15 10 8 22 32 MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz see also waveforms Fig.4 TYPICAL EXTRAPOLATION FORMULA
January 1995
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Philips Semiconductors
Product specification
Quadruple D-type register with 3-state outputs
HEF4076B MSI
VDD V Dynamic power dissipation per package (P) 5 10 15
TYPICAL FORMULA FOR P (W) 2200 fi + (foCL) x VDD2 9300 fi + (foCL) x 24 500 fi + (foCL) x VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)
January 1995
6
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Quadruple D-type register with 3-state outputs HEF4076B MSI

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